1. Field of the Invention
This invention relates to a multi-bit digital-to-analog (hereinafter referred to as D/A) converter with high accuracy.
2. Prior Art
Conventionally, D/A converters having different types of circuit arrangements have been proposed and become commercially available. FIG. 18 schematically shows an example of the circuitry of a 4-bit D/A converter using a ladder circuit. In the D/A converter, voltages generated by the ladder circuit are supplied to an adder circuit via switches which are each turned on and off according to data for conversion, and then synthesized by the adder circuit to be output as a converted voltage.
The conventional D/A converter is capable of converting twelve bits at the maximum without executing a resistance trimming process, but the resistance trimming process is indispensable for production of a D/A converter capable of converting more than twelve bits. However, the resistance trimming process costs a lot and makes it impossible to produce a D/A converter by using a CMOS process.
As a D/A converter having another type of circuit arrangement, there has been proposed a resistor string D/A converter based on a resistor string method. In the resistor string D/A converter, voltages are generated across numerous resistors connected in series, and voltages at respective junctions on the string of the resistors are selectively output as a converted voltage. The D/A converter of this type is capable of highly accurate conversion, and advantageous in that it can be made by a CMOS process. However, the resistor string method also has a drawback of being incapable of realizing a multi-bit D/A converter which converts e.g. twenty-four bits.
It is an object of the present invention to provide a high-accuracy and multi-bit D/A converter which can be produced using a CMOS process.
To attain the above object, the invention provides a digital-to-analog converter comprising a plurality of resistors connected in series, N (N: an integer larger than 1) first switch strings each formed of M (M: an integer larger than 1) switches each having one end thereof connected to a corresponding one of junctions of the plurality of resistors and having respective other ends commonly connected to one of common junctions, a switch control circuit that turns on and off the switches of the first switch strings according to more significant bits of data for conversion, a voltage-generating circuit that generates a voltage corresponding to less significant bits of the data for conversion and outputs the voltage, and an adder/subtractor circuit that carries out addition or subtraction of a voltage at each of the common junctions and an output from the voltage-generating circuit.
Preferably, the voltage-generating circuit comprises a plurality of switches disposed to be turned on and off according to the less significant bits of the data for conversion to output voltages, and a circuit that applies the voltages from the switches to the adder/subtractor circuit through a plurality of weighted resistors.
Alternatively, the voltage-generating circuit comprises a plurality of switches disposed to be turned on and off according to the less significant bits of the data for conversion to output voltages, and a resistor ladder circuit that converts the voltages from the switches to a voltage corresponding to ones of the switches that are turned on.
In another preferred form, the voltage-generating circuit comprises at least one second switch string each formed of a plurality of switches each having one end thereof connected to a corresponding one of the junctions of the plurality of resistors and having respective other ends commonly connected to at least one common junction, a less significant bits-side switch control circuit that turns on and off the switches of the at least one second switch string according to the less significant bits of the data for conversion, and a circuit that applies a voltage at the at least one common junction of the at least one second switch string to the adder/subtractor circuit through a plurality of weighted resistors.
Alternatively, the voltage-generating circuit comprises at least one second switch string each formed of a plurality of switches each having one end thereof connected to a corresponding one of the junctions of the plurality of resistors and having respective other ends commonly connected to at least one common junction, a less significant bits-side switch control circuit that turns on and off the switches of the at least one second switch string according to less significant bits of the data for conversion, and a circuit that applies a voltage at the at least one common junction of the at least one second switch string to the adder/subtractor circuit through a resistor ladder circuit.
Preferably, the switch control circuit turns on and off the switches in a manner such that voltage errors occurring at the common junctions of the first switch strings due to errors in resistance values of the plurality of resistors cancel each other.
Also preferably, the switch control circuit turns on and off the switches in a manner such that voltage errors occurring at the common junctions of the at least one second switch string due to errors in resistance values of the plurality of resistors cancel each other.
According to the above constructions of the present invention, conversion of the more significant bits is performed by the resistor string and the switch matrix, and therefore it is possible to provide a high-accuracy and multi-bit D/A converter which can be produced without such time and labor as required when employing a resistance trimming process. Further, the D/A converter according to the present invention can be produced using a CMOS process, which is advantageous to mass production.
Preferably, the first switch strings comprise first and second switch strings disposed such that voltages at the common junctions are supplied to the adder/subtractor circuit for the addition, and third and fourth switch strings disposed such that voltages at the common junctions are supplied to the adder/subtractor circuit for the subtraction, and the switch control circuit turns on and off the first and second switch strings in a manner such that errors in output voltages of the first and second switch strings cancel each other, and turns on and off the third and fourth switch strings in a manner such that errors in output voltages of the third and fourth switch strings cancel each other.
Also preferably, the at least one second switch string comprise first and second switch strings disposed such that voltages at the common junctions are supplied to the adder/subtractor circuit for the addition, and third and fourth switch strings disposed such that voltages at the common junctions are supplied to the adder/subtractor circuit for the subtraction, and the less significant bits-side switch control circuit turns on and off the first and second switch strings of the at least one second switch string in a manner such that errors in output voltages of the first and second switch strings cancel each other, and turns on and off off the third and fourth switch strings of the at least one second switch string in a manner such that errors in output voltages of the third and fourth switch strings cancel each other.
According to the above constructions of the present invention, it is possible to minimize the conversion error due to resistance errors.
The above and other objects, features, and advantages of the invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawing.